8-Bit Serial-Input/Serial or Parallel-Output Shift Register with ...

SEMICONDUCTOR TECHNICAL DATA 

 

 

 

High–Performance Silicon–Gate CMOS 

The MC54/74HC595A is identical in pinout to the LS595. The device 

inputs are compatible with standard CMOS outputs; with pullup resistors, 

they are compatible with LSTTL outputs. 

The HC595A consists of an 8–bit shift register and an 8–bit D–type latch 

with three–state parallel outputs. The shift register accepts serial data and 

provides a serial output. The shift register also provides parallel data to the 

8–bit latch. The shift register and latch have independent clock inputs. This 

device also has an asynchronous reset for the shift register. 

The HC595A directly interfaces with the Motorola SPI serial data port on 

CMOS MPUs and MCUs. 

• Output Drive Capability: 15 LSTTL Loads 

• Outputs Directly Interface to CMOS, NMOS, and TTL 

• Operating Voltage Range: 2.0 to 6.0 V 

• Low Input Current: 1.0 µA 

• High Noise Immunity Characteristic of CMOS Devices 

• In Compliance with the Requirements Defined by JEDEC Standard 

No. 7A 

• Chip Complexity: 328 FETs or 82 Equivalent Gates 

• Improvements over HC595 

— Improved Propagation Delays 

— 50% Lower Quiescent Power 

— Improved Input Noise and Latchup Immunity 

 

16 

16 

1 

16 

16 

1 

1 

1 

N SUFFIX 

PLASTIC PACKAGE 

CASE 648–08 

D SUFFIX 

SOIC PACKAGE 

CASE 751B–05 

ORDERING INFORMATION 

MC54HCXXXAJ 

MC74HCXXXAN 

MC74HCXXXAD 

MC74HCXXXADT 

J SUFFIX 

CERAMIC PACKAGE 

CASE 620–10 

DT SUFFIX 

TSSOP PACKAGE 

CASE 948F–01 

Ceramic 

Plastic 

SOIC 

TSSOP 

LOGIC DIAGRAM 

PIN ASSIGNMENT 

SERIAL 

DATA 

INPUT 

A 

14 

SHIFT 

REGISTER 

LATCH 

15 

QA 

1 

QB 

2 

QC 

3 

QD 

4 

QE 

5 

QF 

6 

QG 

7 

QH 

PARALLEL 

DATA 

OUTPUTS 

QB 

QC 

QD 

QE 

QF 

QG 

QH 

GND 

1 

2 

3 

4 

5 

6 

7 

8 

16 

15 

14 

13 

12 

11 

10 

9 

VCC 

QA 

A 

OUTPUT ENABLE 

LATCH CLOCK 

SHIFT CLOCK 

RESET 

SQH 

SHIFT 

CLOCK 

RESET 

LATCH 

CLOCK 

OUTPUT 

ENABLE 

11 

10 

12 

13 

9 

SQH 

SERIAL 

DATA 

OUTPUT 

VCC = PIN 16 

GND = PIN 8 

3/97 

© Motorola, Inc. 1997 

1 REV 7

MC54/74HC595A 

MAXIMUM RATINGS* 

Parameter 

Value 

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 

SymbolÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 


VCC DC Supply Voltage 

ÎÎÎÎÎÎ 

(Referenced to 

ÎÎÎ 

GND) 

– 0.5 

ÎÎÎ 

to + 7.0 V 

V in DC Input Voltage (Referenced to GND) 

ÎÎÎÎÎÎV 

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 

ÎÎÎ 

ÎÎÎ 


Vout DC Output Voltage (Referenced 

ÎÎÎÎÎÎ 

to GND) 

ÎÎÎ 

– 0.5 to 0.5ÎÎÎ 

VCC + V 

I in DC Input Current, per Pin 

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎmA 


ÎÎÎ 

ÎÎÎ 

Unit 

– 0.5 to VCC + 0.5ÎÎÎ 

± 20 

ÎÎÎ 

I ÎÎÎ 

out DC Output Current, per 

ÎÎÎÎÎÎ 

Pin 

± ÎÎÎ 

35 mA 

I CC DC Supply Current, VCC and GND Pins 

ÎÎÎÎÎÎmA 


ÎÎÎ 


ÎÎÎ 

± 75 

ÎÎÎ 

PD Power ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 

Dissipation in Still Air, Plastic or Ceramic DIP† ÎÎÎÎÎÎ 

750 ÎÎÎ 

ÎÎÎ 

mW 

ÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎ 

T stg 

TL 

Storage Temperature 

SOIC Package† 

TSSOP Package† 

Lead Temperature, 1 mm from Case for 10 Seconds 

(Plastic DIP, SOIC or TSSOP Package) 

(Ceramic DIP) 

ÎÎÎ 

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 

ÎÎÎ 


500 

450 

– 65 to + 150 

ÎÎÎ 

ÎÎÎÎÎÎ 

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎ 

ÎÎÎÎÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 

ÎÎÎ 

260 

300 

* Maximum Ratings are those values beyond which damage to the device may occur. 

Functional operation should be restricted to the Recommended Operating Conditions. 

†Derating — Plastic DIP: – 10 mW/ C from 65 to 125 C 

Ceramic DIP: – 10 mW/ C from 100 to 125 C 

SOIC Package: – 7 mW/ C from 65 to 125 C 

TSSOP Package: – 6.1 mW/ C from 65 to 125 C 

For high frequency or heavy load considerations, see Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). 

RECOMMENDED OPERATING CONDITIONS 

Symbol 

VCC 

Parameter 

DC Supply Voltage (Referenced to GND) 

ÎÎÎÎ 

ÎÎÎ 


ÎÎÎ ÎÎÎ 

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 


Vin, Vout DC Input Voltage, Output Voltage 

VCCÎÎÎ 

0 ÎÎÎ 

V 

(Referenced to GND) 

C 

C 

Min ÎÎÎ Max ÎÎÎ Unit 

2.0 ÎÎÎ 

6.0 ÎÎÎ 

V 

This device contains protection 

circuitry to guard against damage 

due to high static voltages or electric 

fields. However, precautions must 

be taken to avoid applications of any 

voltage higher than maximum rated 

voltages to this high–impedance circuit. 

For proper operation, Vin and 

Vout should be constrained to the 

range GND (Vin or Vout) VCC. 

Unused inputs must always be 

tied to an appropriate logic voltage 

level (e.g., either GND or VCC). 

Unused outputs must be left open. 


ÎÎÎ ÎÎÎ 

ÎÎÎÎ 

ÎÎÎ 

TA 

tr, tf 

Operating Temperature, All Package Types 

Input Rise and Fall Time 

(Figure 1) 

VCC = 2.0 V 

VCC = 4.5 V 

– 55 + 125 C 

ÎÎÎ ÎÎÎ 

ÎÎÎ ÎÎÎ 

ÎÎÎÎ 

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 

ÎÎÎÎ 

VCC = 6.0 V 0 400 

0 

0 

1000 

500 

ns 

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) 


ÎÎÎÎ 

ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 

ÎÎÎÎ 

ÎÎÎÎÎÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 

Symbol 

Parameter 

Test Conditions 

i 

Unit 

VIH 

Minimum High–Level Input 

Voltage 

Vout = 0.1 V or VCC – 0.1 V 

|Iout| 20 µA 

VCC 

V 

Guaranteed Limit 

ÎÎÎÎ 

ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎ 

ÎÎÎÎÎÎ 

ÎÎÎÎ ÎÎÎÎ 

ÎÎÎ 

ÎÎÎÎÎÎÎÎÎÎÎ 

ÎÎÎÎ 



ÎÎÎÎ 

VIL 

Maximum Low–Level Input 

Voltage 

Vout = 0.1 V or VCC – 0.1 V 

|Iout| 20 µA 

ÎÎÎÎ 

ÎÎÎÎÎÎÎÎÎÎÎÎ 



ÎÎÎ ÎÎÎ 

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 

2.0 

3.0 

4.5 

6.0 

– 55 to 

25 C 

1.5 

2.1 

3.15 

4.2 

85 C 

1.5 

2.1 

3.15 

4.2 

125 C 

1.5 

2.1 

3.15 

4.2 

ÎÎÎÎ 




ÎÎÎ ÎÎÎ 


ÎÎÎÎ 



ÎÎÎÎ 

VOH 

Minimum High–Level Output 

Voltage, QA – QH 

Vin = VIH or VIL 

|Iout| 20 µA 

ÎÎÎÎ 


ÎÎÎÎÎÎ 


ÎÎÎ 


ÎÎÎÎ 



ÎÎÎÎ 


|Iout| 2.4 mA 

|Iout| 6.0 mA 

|Iout| 7.8 mA 

ÎÎÎÎ 




ÎÎÎ ÎÎÎ 


2.0 

3.0 

4.5 

6.0 

2.0 

4.5 

6.0 

3.0 

4.5 

6.0 

0.5 

0.9 

1.35 

1.8 

1.9 

4.4 

5.9 

2.48 

3.98 

5.48 

0.5 

0.9 

1.35 

1.8 

1.9 

4.4 

5.9 

2.34 

3.84 

5.34 

0.5 

0.9 

1.35 

1.8 

1.9 

4.4 

5.9 

2.2 

3.7 

5.2 

V 

V 

V 


ÎÎÎÎ 


ÎÎÎÎ 


ÎÎÎÎ 

MOTOROLA 

2 

High–Speed CMOS Logic Data 

DL129 — Rev 6

MC54/74HC595A 

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) 

Symbol 

Parameter 

Test Conditions 


ÎÎÎ 

ÎÎÎÎ 




ÎÎÎÎ 

ÎÎÎ 

ÎÎÎÎ 



ÎÎÎÎ 


VOL 

Maximum Low–Level Output 

Voltage, QA – QH 


|Iout| 20 µA 

ÎÎÎ 

ÎÎÎÎ 

ÎÎÎ ÎÎÎÎ 



ÎÎÎÎ 

ÎÎÎÎ 



|Iout| 2.4 mA 

|Iout| 6.0 mA 

|Iout| 7.8 mA 

VCC 

V 

– 55 to 

25 C 

85 C 

0.1 

0.1 

0.1 

125 C 

0.1 

0.1 

0.1 

ÎÎÎÎ 




ÎÎÎ ÎÎÎ 


VOH 

Minimum High–Level Output 

Voltage, SQH 


IIoutI 20 µA 

ÎÎÎÎ 




ÎÎÎ ÎÎÎ 

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 


|Iout| 2.4 mA 

IIoutI 4.0 mA 

IIoutI 5.2 mA 

ÎÎÎÎ 




ÎÎÎ ÎÎÎ 


ÎÎÎÎ 




ÎÎÎ ÎÎÎ 


ÎÎÎÎ 



ÎÎÎÎ 

VOL 

Maximum Low–Level Output 

Voltage, SQH 


IIoutI 20 µA 

ÎÎÎÎ 


ÎÎÎÎÎÎ 


ÎÎÎ 


ÎÎÎÎ 



ÎÎÎÎ 


|Iout| 2.4 mA 

IIoutI 4.0 mA 

IIoutI 5.2 mA 

ÎÎÎÎ 


ÎÎÎÎÎÎ 


ÎÎÎ 


ÎÎÎÎ 



ÎÎÎÎ 

Iin 

IOZ 

Maximum Input Leakage Current Vin = VCC or GND 


Maximum Three–State Leakage 

Current, QA – QH 

Output in High–Impedance State 

Vin = VIL or VIH 

Vout = VCC or GND 


ÎÎÎÎ 


ÎÎÎÎ 




ICC 

Maximum Quiescent Supply 

Current (per Package) 

Vin = VCC or GND 

lout = 0 µA 

2.0 

4.5 

6.0 

3.0 

4.5 

6.0 

2.0 

4.5 

6.0 

3.0 

4.5 

6.0 

2.0 

4.5 

6.0 

3.0 

4.5 

6.0 

0.1 

0.1 

0.1 

0.26 

0.26 

0.26 

1.9 

4.4 

5.9 

2.98 

3.98 

5.48 

0.1 

0.1 

0.1 

0.26 

0.26 

0.26 

0.33 

0.33 

0.33 

1.9 

4.4 

5.9 

2.34 

3.84 

5.34 

0.1 

0.1 

0.1 

0.33 

0.33 

0.33 

0.4 

0.4 

0.4 

1.9 

4.4 

5.9 

2.2 

3.7 

5.2 

0.1 

0.1 

0.1 

0.4 

0.4 

0.4 

Unit 

ÎÎÎ 

6.0 ± 0.1 ± 1.0 ± 1.0 µA ÎÎÎ 

ÎÎÎÎ 

ÎÎÎÎ 

ÎÎÎ 

6.0 ± 0.5 ± 5.0 ± 10 µA 

ÎÎÎ 

ÎÎÎÎ 

ÎÎÎÎ 

ÎÎÎÎ 




ÎÎÎ ÎÎÎ 


NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D). 


ÎÎÎÎ 

6.0 

4.0 

40 

160 

V 

V 

V 

µA 


ÎÎÎÎ 

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) 

ÎÎÎÎ 


ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 



ÎÎÎ 

Symbol 

fmax 

Parameter 

Maximum Clock Frequency (50% Duty Cycle) 

(Figures 1 and 7) 

VCC 

V 


ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 


tPLH, 

tPHL 

Maximum Propagation Delay, Shift Clock to SQH 


ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 


2.0 

3.0 

4.5 

6.0 

– 55 to 

25 C 

6.0 

15 

30 

35 

85 C 

4.8 

10 

24 

28 

125 C 

4.0 

8.0 

20 

24 

ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 

ÎÎÎÎ ÎÎÎÎÎÎ 

ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

tPHL 

Maximum Propagation Delay, Reset to SQH 


ÎÎÎÎ 

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ 

ÎÎÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

tPLH, 

tPHL 

Maximum Propagation Delay, Latch Clock to QA – QH 


ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 


tPLZ, 

tPHZ 

Maximum Propagation Delay, Output Enable to QA – QH 


ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

tPZL, 

tPZH 

Maximum Propagation Delay, Output Enable to QA – QH 


ÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

2.0 

3.0 

4.5 

6.0 

2.0 

3.0 

4.5 

6.0 

2.0 

3.0 

4.5 

6.0 

2.0 

3.0 

4.5 

6.0 

2.0 

3.0 

4.5 

6.0 

140 

100 

28 

24 

145 

100 

29 

25 

140 

100 

28 

24 

150 

100 

30 

26 

135 

90 

27 

23 

175 

125 

35 

30 

180 

125 

36 

31 

175 

125 

35 

30 

190 

125 

38 

33 

170 

110 

34 

29 

210 

150 

42 

36 

220 

150 

44 

38 

210 

150 

42 

36 

225 

150 

45 

38 

205 

130 

41 

35 

Unit 

MHz 

ns 

ns 

ns 

ns 

ns 

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 


DL129 — Rev 6 

3 MOTOROLA

MC54/74HC595A 

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) 

Symbol 

Parameter 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 


tTLH, 

tTHL 

Maximum Output Transition Time, QA – QH 


ÎÎÎ 

ÎÎÎÎ 

ÎÎÎ ÎÎÎÎ 


ÎÎÎÎ 

ÎÎÎÎ 

ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 

tTLH, 

tTHL 

Maximum Output Transition Time, SQH 


VCC 

V 

– 55 to 

25 C 

ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 


2.0 

3.0 

4.5 

6.0 

60 

23 

12 

10 

85 C 

75 

27 

15 

13 

125 C 

90 

31 

18 

15 

ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

ÎÎÎÎ 

Cin 


Maximum Input Capacitance 

ÎÎÎÎ 

— 10 10 ÎÎÎÎÎÎ 

ÎÎÎÎ 

10 pF 

ÎÎÎ 


Maximum Three–State Output Capacitance (Output in ÎÎÎÎ — ÎÎÎ 15 ÎÎÎÎ 15 ÎÎÎÎ 15 ÎÎÎ pF 

Cout 

High–Impedance State), QA – QH 

NOTE: For propagation delays with loads other than 50 pF, and information on typical parametric values, see Chapter 2 of the Motorola High– 

Speed CMOS Data Book (DL129/D). 

ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

Typical @ 25°C, VCC = 5.0 V 

CPD Power Dissipation i i Capacitance (Per Package)* 300 pF 

* Used to determine the no–load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC. For load considerations, see Chapter 2 of the 

Motorola High–Speed CMOS Data Book (DL129/D). 

2.0 

3.0 

4.5 

6.0 

75 

27 

15 

13 

95 

32 

19 

16 

110 

36 

22 

19 

Unit 

ns 

ns 

TIMING REQUIREMENTS (Input tr = tf = 6.0 ns) 

Symbol 

Parameter 

ÎÎÎÎ 





ÎÎÎ 

tsu 

Minimum Setup Time, Serial Data Input A to Shift Clock 

(Figure 5) 

VCC 

V 

25 C to 

– 55 C 


85 C 

125 C 

ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 


tsu 

Minimum Setup Time, Shift Clock to Latch Clock 

(Figure 6) 

ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

th 

Minimum Hold Time, Shift Clock to Serial Data Input A 

(Figure 5) 

ÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

trec 

Minimum Recovery Time, Reset Inactive to Shift Clock 

(Figure 2) 

ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

tw 

Minimum Pulse Width, Reset 

(Figure 2) 

ÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

tw 

Minimum Pulse Width, Shift Clock 

(Figure 1) 

ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

tw 

Minimum Pulse Width, Latch Clock 

(Figure 6) 

ÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎ 

ÎÎÎÎ 


ÎÎÎÎ 

tr, tf 

Maximum Input Rise and Fall Times 

(Figure 1) 

ÎÎÎÎ 

ÎÎÎÎÎÎ 


ÎÎÎÎÎÎ 

ÎÎÎÎ 



ÎÎÎÎ 

ÎÎÎÎ 


ÎÎÎ 

6.0 400 400 400 

2.0 

3.0 

4.5 

6.0 

2.0 

3.0 

4.5 

6.0 

2.0 

3.0 

4.5 

6.0 

2.0 

3.0 

4.5 

6.0 

2.0 

3.0 

4.5 

6.0 

2.0 

3.0 

4.5 

6.0 

2.0 

3.0 

4.5 

6.0 

2.0 

3.0 

4.5 

50 

40 

10 

9.0 

75 

60 

15 

13 

5.0 

5.0 

5.0 

5.0 

50 

40 

10 

9.0 

60 

45 

12 

10 

50 

40 

10 

9.0 

50 

40 

10 

9.0 

1000 

800 

500 

65 

50 

13 

11 

95 

70 

19 

16 

5.0 

5.0 

5.0 

5.0 

65 

50 

13 

11 

75 

60 

15 

13 

65 

50 

13 

11 

65 

50 

13 

11 

1000 

800 

500 

75 

60 

15 

13 

110 

80 

22 

19 

5.0 

5.0 

5.0 

5.0 

75 

60 

15 

13 

90 

70 

18 

15 

75 

60 

15 

13 

75 

60 

15 

13 

1000 

800 

500 

Unit 

ns 

ns 

ns 

ns 

ns 

ns 

ns 

ns 


ÎÎÎÎ 

MOTOROLA 

4 


DL129 — Rev 6 

ÎÎÎÎ 

ÎÎÎÎ 



ÎÎÎ

MC54/74HC595A 

Operation 

Reset 

Serial 

Input 

A 

Inputs 

Shift 

Clock 

FUNCTION TABLE 

Latch 

Clock 

Output 

Enable 

Shift 

Register 

Contents 

Resulting Function 

Latch 

Register 

Contents 

Serial 

Output 

SQH 

Reset shift register L X X L, H, ↓ L L U L U 

Parallel 

Outputs 

QA – QH 

Shift data into shift 

register 

H D ↑ L, H, ↓ L D → SRA; 

SRN → SRN+1 

U SRG → SRH U 

Shift register remains 

unchanged 

Transfer shift register 

contents to latch register 

Latch register remains 

unchanged 

H X L, H, ↓ L, H, ↓ L U U U U 

H X L, H, ↓ ↑ L U SRN → LRN U SRN 

X X X L, H, ↓ L * U * U 

Enable parallel outputs X X X X L * ** * Enabled 

Force outputs into high 

impedance state 

X X X X H * ** * Z 

SR = shift register contents D = data (L, H) logic level ↑ = Low–to–High * = depends on Reset and Shift Clock inputs 

LR = latch register contents U = remains unchanged ↓ = High–to–Low ** = depends on Latch Clock input 

PIN DESCRIPTIONS 

INPUTS 

A (Pin 14) 

Serial Data Input. The data on this pin is shifted into the 

8–bit serial shift register. 

CONTROL INPUTS 

Shift Clock (Pin 11) 

Shift Register Clock Input. A low– to–high transition on this 

input causes the data at the Serial Input pin to be shifted into 

the 8–bit shift register. 

Reset (Pin 10) 

Active–low, Asynchronous, Shift Register Reset Input. A 

low on this pin resets the shift register portion of this device 

only. The 8–bit latch is not affected. 

Latch Clock (Pin 12) 

Storage Latch Clock Input. A low–to–high transition on this 

input latches the shift register data. 

Output Enable (Pin 13) 

Active–low Output Enable. A low on this input allows the 

data from the latches to be presented at the outputs. A high 

on this input forces the outputs (QA–QH) into the high– 

impedance state. The serial output is not affected by this 

control unit. 

OUTPUTS 

QA – QH (Pins 15, 1, 2, 3, 4, 5, 6, 7) 

Noninverted, 3–state, latch outputs. 

SQH (Pin 9) 

Noninverted, Serial Data Output. This is the output of the 

eighth stage of the 8–bit shift register. This output does not 

have three–state capability. 


DL129 — Rev 6 

5 MOTOROLA

MC54/74HC595A 

SWITCHING WAVEFORMS 

SHIFT 

CLOCK 

tr 

90% 

50% 

10% 

tw 

tf 

VCC 

GND 

RESET 

tPHL 

50% 

tw 

VCC 

GND 

OUTPUT 

SQH 

90% 

50% 

10% 

tPLH 

1/fmax 

tTLH 

tPHL 

tTHL 

OUTPUT 

SQH 

SHIFT 

CLOCK 

50% 

trec 

50% 

VCC 

GND 

Figure 1. Figure 2. 

LATCH 

CLOCK 

QA–QH 

OUTPUTS 

90% 

50% 

10% 

50% 

tPLH 

tTLH 

tPHL 

tTHL 

VCC 

GND 

OUTPUT 

ENABLE 

OUTPUT Q 

OUTPUT Q 

50% 

tPZL 

50% 

tPZH 

50% 

tPLZ 

tPHZ 

10% 

90% 

VCC 

GND 

HIGH 

IMPEDANCE 

VOL 

VOH 

HIGH 

IMPEDANCE 

Figure 3. 

Figure 4. 

SERIAL 

INPUT A 

LATCH 

CLOCK 

VALID 

50% 

tsu th 

50% 

VCC 

GND 

VCC 

GND 

SHIFT 

CLOCK 

LATCH 

CLOCK 

50% 

tsu 

50% 

tw 

VCC 

GND 

VCC 

GND 

Figure 5. 

Figure 6. 

TEST CIRCUITS 

TEST POINT 

TEST POINT 

DEVICE 

UNDER 

TEST 

OUTPUT 

CL* 

DEVICE 

UNDER 

TEST 

OUTPUT 

1 kΩ 

CL* 

CONNECT TO VCC WHEN 

TESTING tPLZ AND tPZL. 

CONNECT TO GND WHEN 

TESTING tPHZ AND tPZH. 

* Includes all probe and jig capacitance 

* Includes all probe and jig capacitance 

Figure 7. Figure 8. 

MOTOROLA 

6 


DL129 — Rev 6

MC54/74HC595A 

EXPANDED LOGIC DIAGRAM 

OUTPUT 

ENABLE 

13 

LATCH 

CLOCK 

12 

SERIAL 

DATA 

INPUT A 

14 

D 

SRA 

Q 

D 

LRA 

Q 

15 

QA 

R 

D 

Q 

D 

Q 

1 

QB 

SRB 

LRB 

R 

D 

Q 

D 

Q 

2 

QC 

R 

SRC 

LRC 

D 

Q 

D 

Q 

3 

QD 

SRD 

R 

D 

Q 

D 

LRD 

Q 

4 

QE 

PARALLEL 

DATA 

OUTPUTS 

R 

SRE 

LRE 

D 

Q 

D 

Q 

5 

QF 

R 

SRF 

LRF 

D 

Q 

D 

Q 

6 

QG 

SRG 

LRG 

R 

SHIFT 

CLOCK 

11 

D 

SRH 

Q 

D 

LRH 

Q 

7 

QH 

R 

RESET 

10 

9 

SERIAL 

DATA 

OUTPUT SQH 


DL129 — Rev 6 

7 MOTOROLA

MC54/74HC595A 

TIMING DIAGRAM 

SHIFT 

CLOCK 

SERIAL DATA 

INPUT A 

RESET 

LATCH 

CLOCK 

OUTPUT 

ENABLE 

QA 

QB 

QC 

QD 

QE 

QF 

QG 

QH 

SERIAL DATA 

OUTPUT SQH 

NOTE: 

implies that the output is in a high–impedance 

state. 

MOTOROLA 

8 


DL129 — Rev 6

MC54/74HC595A 

16 

9 

–A 

– 

1 8 

–B 

– 

C 

OUTLINE DIMENSIONS 

J SUFFIX 

CERAMIC PACKAGE 

CASE 620–10 

ISSUE V 

L 

NOTES: 

1. DIMENSIONING AND TOLERANCING PER 

ANSI Y14.5M, 1982. 

2. CONTROLLING DIMENSION: INCH. 

3. DIMENSION L TO CENTER OF LEAD WHEN 

FORMED PARALLEL. 

4. DIM F MAY NARROW TO 0.76 (0.030) WHERE 

THE LEAD ENTERS THE CERAMIC BODY. 

–T 

SEATING – 

PLANE 

F 

E 

N 

G 

D 16 PL 

0.25 (0.010) M T A 

S 

K 

M 

J 16 PL 

0.25 (0.010) M T B 

S 

DIM 

A 

B 

C 

D 

E 

F 

G 

J 

K 

L 

M 

N 

INCHES 

MIN MAX 

0.750 0.785 

0.240 0.295 

— 0.200 

0.015 0.020 

0.050 BSC 

0.055 0.065 

0.100 BSC 

0.008 0.015 

0.125 0.170 

0.300 BSC 

0° 15° 

0.020 0.040 

MILLIMETERS 

MIN MAX 

19.05 19.93 

6.10 7.49 

— 5.08 

0.39 0.50 

1.27 BSC 

1.40 1.65 

2.54 BSC 

0.21 0.38 

3.18 4.31 

7.62 BSC 

0° 

0.51 

15° 

1.01 

16 

–A 

– 

9 

B 

1 8 

H 

G 

F 

S 

C 

K 

–T 

– 

SEATING 

PLANE 

D 16 PL 

0.25 (0.010) M T A M 

N SUFFIX 

PLASTIC PACKAGE 

CASE 648–08 

ISSUE R 

J 

L 

M 

NOTES: 

1. DIMENSIONING AND TOLERANCING PER ANSI 

Y14.5M, 1982. 

2. CONTROLLING DIMENSION: INCH. 

3. DIMENSION L TO CENTER OF LEADS WHEN 

FORMED PARALLEL. 

4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 

5. ROUNDED CORNERS OPTIONAL. 

DIM 

A 

B 

C 

D 

F 

G 

H 

J 

K 

L 

M 

S 

INCHES 

MIN MAX 

0.740 0.770 

0.250 0.270 

0.145 0.175 

0.015 0.021 

0.040 0.070 

0.008 

0.110 

0.295 

0° 

0.020 

0.100 BSC 

0.050 BSC 

0.015 

0.130 

0.305 

10° 

0.040 

MILLIMETERS 

MIN MAX 

18.80 19.55 

6.35 6.85 

3.69 4.44 

0.39 0.53 

1.02 1.77 

2.54 BSC 

1.27 BSC 

0.21 

2.80 

7.50 

0° 

0.51 

0.38 

3.30 

7.74 

10° 

1.01 

–T 

SEATING – 

PLANE 

16 

1 8 

G 

D 16 PL 

–A 

– 

9 

–B 

– 

K 

C 

0.25 (0.010) M T B S A S 

D SUFFIX 

PLASTIC SOIC PACKAGE 

CASE 751B–05 

ISSUE J 

P 8 PL 

0.25 (0.010) M B 

M 

M 

R X 45° 

J 

F 

NOTES: 


Y14.5M, 1982. 

2. CONTROLLING DIMENSION: MILLIMETER. 

3. DIMENSIONS A AND B DO NOT INCLUDE 

MOLD PROTRUSION. 

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) 

PER SIDE. 

5. DIMENSION D DOES NOT INCLUDE DAMBAR 

PROTRUSION. ALLOWABLE DAMBAR 

PROTRUSION SHALL BE 0.127 (0.005) TOTAL 

IN EXCESS OF THE D DIMENSION AT 

MAXIMUM MATERIAL CONDITION. 

DIM 

A 

B 

C 

D 

F 

G 

J 

K 

M 

P 

R 

MILLIMETERS 

MIN MAX 

9.80 10.00 

3.80 4.00 

1.35 1.75 

0.35 0.49 

0.40 1.25 

0.19 

0.10 

0° 

5.80 

0.25 

INCHES 

MIN MAX 

0.386 0.393 

0.150 0.157 

0.054 0.068 

0.014 0.019 

0.016 0.049 

1.27 BSC 0.050 BSC 

0.25 

0.25 

7° 

6.20 

0.50 

0.008 

0.004 

0° 

0.229 

0.010 

0.009 

0.009 

7° 

0.244 

0.019 


DL129 — Rev 6 

9 MOTOROLA

MC54/74HC595A 

OUTLINE DIMENSIONS 

DT SUFFIX 

PLASTIC TSSOP PACKAGE 

CASE 948F–01 

ISSUE O 

0.15 (0.006) T 

0.15 (0.006) T 

0.10 (0.004) 

–T– SEATING 

PLANE 

L 

U 

PIN 1 

IDENT. 

U 

D 

S 

S 

2X L/2 

C 

16X K REF 

0.10 (0.004) M T U S V S 

16 9 

1 8 

A 

–V– 

G 

B 

–U– 

H 

N 

N 

J 

J1 

F 

DETAIL E 

DETAIL E 

K 

K1 

ÇÇ ÉÉ 

SECTION 

ÉÉN–N 

ÇÇ 

0.25 (0.010) 

M 

–W– 

NOTES: 


Y14.5M, 1982. 

2. CONTROLLING DIMENSION: MILLIMETER. 

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. 

PROTRUSIONS OR GATE BURRS. MOLD FLASH OR 

GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER 

SIDE. 

4. DIMENSION B DOES NOT INCLUDE INTERLEAD 

FLASH OR PROTRUSION. INTERLEAD FLASH OR 

PROTRUSION SHALL NOT EXCEED 

0.25 (0.010) PER SIDE. 

5. DIMENSION K DOES NOT INCLUDE DAMBAR 

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION 

SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K 

DIMENSION AT MAXIMUM MATERIAL CONDITION. 

6. TERMINAL NUMBERS ARE SHOWN FOR 

REFERENCE ONLY. 

7. DIMENSION A AND B ARE TO BE DETERMINED AT 

DATUM PLANE –W–. 

MILLIMETERS INCHES 

DIM MIN MAX MIN MAX 

A 4.90 5.10 0.193 0.200 

B 4.30 4.50 0.169 0.177 

C ––– 1.20 ––– 0.047 

D 0.05 0.15 0.002 0.006 

F 0.50 0.75 0.020 0.030 

G 0.65 BSC 0.026 BSC 

H 0.18 0.28 0.007 0.011 

J 0.09 0.20 0.004 0.008 

J1 0.09 0.16 0.004 0.006 

K 0.19 0.30 0.007 0.012 

K1 0.19 0.25 0.007 0.010 

L 6.40 BSC 0.252 BSC 

M 0 8 0 8 

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding 

the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and 

specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola 

data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” 

must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of 

others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other 

applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury 

or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola 

and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees 

arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that 

Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal 

Opportunity/Affirmative Action Employer. 

Mfax is a trademark of Motorola, Inc. 

How to reach us: 

USA / EUROPE / Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, 6F Seibu–Butsuryu–Center, 

P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 81–3–3521–8315 

Mfax: RMFAX0@email.sps.mot.com – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 

– US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 

INTERNET: http://www.mot.com/SPS/ 

MOTOROLA 

◊ 

10 

MC74HC595A/D 


DL129 — Rev 6

8-Bit Serial-Input/Serial or Parallel-Output Shift Register with ...

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?