3.4 Addressing modes Specify the operand to be used. To generate an address, a segment register is used also. Immediate addressing: the operand is a number.

Presentation on theme: "3.4 Addressing modes Specify the operand to be used. To generate an address, a segment register is used also. Immediate addressing: the operand is a number."— Presentation transcript:

1 3.4 Addressing modes Specify the operand to be used. To generate an address, a segment register is used also. Immediate addressing: the operand is a number included in the instruction body. Register addressing: the operand is a register. MOV CX,1024 ADD AL , BL Direct addressing: the operand address is a number in [] or the value of a symbol (no [].) MOV AX,[3000] MOV BL,COUNTER Register indirect addressing: the register enclosed in [ ] specifies the operand address. Indexed addressing: the operand address is the sum of the value of the index register and a number, both enclosed in [ ]. MOV BX,[SI] The displacement is a signed 2’s complement byte or word MOV BX,[ SI + 10] MOV CL,[ BP - 4] Based addressing: is similar to indexed, but using BP (base pointer) register. Based-indexed addressing: the operand address is the sum of the values of BP and one of the index registers (SI or DI). MOV DS:[ BP + DI],AX Segment overriding Based-indexed with displacement addressing: ads to the former an offset value. MOV DL,[ BP][ DI + 2] or MOV DL,[ BP + DI + 2] Port addressing: used by input/output instructions. The address of the source port for IN or destination port for OUT is a number or a register content. OUT 80H , AL IN AL, DX

2 3.5 The Processor Flags (Condition Codes)
CF PF AF ZF SF TF IF DF OF IOPL NT Carry Flag Parity Flag Auxiliary carry Flag Zero Flag Sign Flag Trace Flag Interrupt enable Flag Direction Flag Overflow Flag I/O Priority Level Nested Task Contains Carry out of MSB of result Indicates if result has even parity Contains Carry out of bit 3 in AL Indicates if result equals zero Indicates if result is negative Provides a single step capability for debugging Enables/disables interrupts Controls pointer updating during string operations Indicates that an overflow occurred in result Priority level of current task (two bits) Indicates if current task is nested Condition Code half Additional Flags

3 3.5 The Processor Flags (Condition Codes)
Sign (Bit 7) Represent the sign (2’s complement) of the last arithmetical or logical operation. The MSB (Most Significant Bit) of the last arithmetical or logical operation result. The processor doesn’t knows if the result is to be interpreted as “signed” or “unsigned”. S flag is always generated. It is the programmer responsibility to test or not the S flag. Bit 7 for byte operation Bit 15 for word operation Bit 31 for double-word operation CMP (Compare) instruction is a subtraction without a saved result. Sign bit is affected. Not affected by other types of instructions (i.e. MOV, JMP, etc) Examples: Flag not affected (keeps the value corresponding to the previous arithmetical operation). AL S MOV AL,3FH X INC AL AX S MOV AX,7FFFH X INC AX

4 3.5 The Processor Flags (Condition Codes)
Zero (Bit 6) Set (1) if the result of the last arithmetical or logical operation was 0. for byte operation for word operation for double-word operation CMP (Compare) instruction is a subtraction without a saved result. Zero bit is affected. Not affected by other types of instructions (i.e. MOV, JMP, etc) Example: Flag not affected (keeps the value corresponding to the previous arithmetical operation). AL Z MOV AL, X DEC AL DEC AL DEC AL DEC AL DEC AL result not 0 result = 0

5 3.5 The Processor Flags (Condition Codes)
Carry (Bit 0) An additional bit for some shift or rotate logical operations. The carry out or borrow out from MSB in the last arithmetical operation. Bit 7 for byte operation Bit 15 for word operation Bit 31 for double-word operation CMP (Compare) instruction is a subtraction without a saved result. Carry bit is affected. Not affected by other types of instructions (i.e. MOV, JMP, etc) Examples: Flag not affected (keeps the value corresponding to the previous arithmetical operation). AL C MOV AL,0FFH X INC AL AL C MOV AL,0AAH X RCL AL X 1 AX C MOV AX,0000H X DEC AX Rotate Left trough Carry

6 3.5 The Processor Flags (Condition Codes)
Auxiliary Carry (Bit 4) The carry out from bit 3 to bit 4 in the last arithmetical operation. Used by Decimal adjust. Not directly tested in an conditional instruction. Parity (Bit 2) Set (1) if an even number of bits in the lower 8 of the result are “1”. Not affected by other types of instructions (i.e. MOV, JMP, etc) Examples: AL P MOV AL,0FFH Even number of “1”s AL P MOV A,07H Odd number of “1”s