Immediate Addressing Mode

Presentation on theme: "Immediate Addressing Mode"— Presentation transcript:

1 Immediate Addressing Mode
Data for the instruction is part of the instruction itself No need to calculate any address Limited range of operands: for n bit fields, -2^(n-1) to +(2^(n-1)-1)

2 Immediate addressing mode
Example: lda 123 *** 123 Op code Memory No memory access needed IR ACC data : *** Note we have used the lda instruction as an example to maintain consistency and to limit the number of operands to one only

3 Direct Addressing mode
Example: lda [123] *** Opcode 456 Memory . data address IR ACC 123 *** Other asm notations or formats may be used

4 Indirect addressing mode
Example: lda [[123]] 456 : 789 Memory Opcode Address of pointer Address of data data 123 IR ACC

5 Register (direct) addressing mode (continued…)
Example: lda R2 Op code address of R2 1234 Address of data data IR R1 R2 R3 R4 ACC Memory : No memory access needed

6 Register Indirect Addressing
Example: lda [R1] Memory IR Op code Address of R1 the instruction points to a CPU register register contains memory address R1 123 456 123 R2 R3 R4 CPU Registers data ACC 456

7 Displacement Addressing
constant Example: lda [ R1 + 8 ] Memory IR Op code Address of R1 8 Memory address Register address + Index 456 128 R 1 120 R 2 CPU registers data ACC 456

8 Address of the next instruction
Relative Addressing Example: jump 4 Memory Opcode IR 4 Address of the next instruction + Next instruction 124 …... PC 120

9 RISC Stands for Reduced Instruction Set Computers
A concept or philosophy of machine design; not a set of architectural features Underlying idea is to reduce the number and complexity of instructions New RISC computers may have some instruction that are quite complex

10 Features of RISC machines
One instruction per clock period All instructions have the same size CPU accesses memory only for Load and Store operations Simple and few addressing modes

11 CISC Complex Instruction Set Computers

12 Features of CISC machines
More work per instruction Wide variety of addressing modes Variable instruction lengths and execution times per instruction CISC machines attempt to reduce the “semantic gap”

13 Disadvantages of CISC Clock period, T, cannot be reduced beyond a certain limit Complex addressing modes delay operand fetch from memory Difficult to make efficient use of speedup techniques

14 Features of RISC machines
Less work per instruction Improved usage of delay slots Efficient usage of Pro-fetching and Speculative Execution Techniques