One of the most common circuit structures, four-guadrant analog multipliers (FQAM) are freguently preferred for modulation, phase shifting, adaptive filtering, neural network applications. In this study, an FQAM design is presented using dynamic threshold voltage MOSFET (DTMOS) technology. Various analyses were performed to evaluate the function of the proposed multiplier. Power consumption is limited by selecting [+ or -]0.2 V supply voltage. The power consumption of the circuit is calculated as 37 nVV. The maximum amplitude of the input signal is 0.1 V. The bandwidth of the multiplier is 3.23 MHz. The total harmonic distortion (THD) of the output signal at the maximum value of the input signal and at a freguency of 100 kHz is around 1.2%. Intermodulation products were calculated to analyze the linearity of the circuit. The changes in DC and AC transfer characteristics according to temperature changes were investigated. Monte Carlo analysis was performed to verify the circuit's robustness against variation of the circuit parameters. In summary, low power consumption and THD, and insensitive of temperature variations are the outstanding features of the circuit when compared with the literature. Keywords: Analog multipliers, DTMOS, low power, low voltage